Ferroelectric memory devices, like other semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) cell configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically include one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices. The access transistor in a 1T1C configuration operates to selectively connect one terminal of the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage and the other capacitor terminal being connected to a plateline pulse during read operations.
The ferroelectric memory cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of platelines and wordlines by address decoding circuitry. Such devices are typically organized internally into blocks, sections, segments, rows and columns. When a data word is read, the cell data from the corresponding bit in each of the columns is sensed using individual sense amplifiers associated with the individual data cell columns.
Data in a ferroelectric memory cell is read by coupling complementary input terminals of a differential sense amp with one terminal of the cell capacitor a reference voltage. The other terminal of the capacitor is connected to a plateline pulse. The dipole switching in the ferroelectric capacitor resulting from the field across the ferroelectric capacitor terminals causes a switching current to flow, creating a differential voltage on the bitline pair coupled with the sense amp terminals. The reference voltage is typically supplied at an intermediate voltage between a voltage (V“0”) associated with a capacitor charged to a binary “0” and that of the capacitor charged to a binary “1” (V“1”). The sense amp senses the differential voltage across the terminals and latches a voltage indicative of whether the target cell was programmed to a binary “0” or to a “1”. The resulting amplified differential voltage at the sense amp terminals represents the data stored in the cell, which is applied to a pair of local IO lines. The sense amp drives one of the local IO lines to a different voltage state, by which the read data state is passed to an IO buffer circuit. The data is then restored to the ferroelectric cell capacitor, as the read operation is destructive.
In a write operation, the complimentary sense amp and bitline terminals are connected to the local IO lines, which are driven to opposite voltage states depending on the data to be written. The wordline turns on the cell access transistor, coupling one of the ferroelectric capacitor terminals to one of the bitlines for storage of the write data into the cell capacitor, and the other capacitor terminal is connected to a plateline pulse. The applied field across the ferroelectric material in the cell capacitor provides dipole switching by which the cell is programmed according to the write data from the local IO. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local IO lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the memory device (e.g., row decoders providing plateline signals and column decoders providing wordline signals to the access transistors in a 1T1C configuration).
Ferroelectric devices achieve low voltage, low power, non-volatile memory with high density, particularly applicable in scaled CMOS technologies, providing density and operational speeds on the order of DRAM along with the non-volatility of Flash memory. In many commercial applications, non-volatile memories must be able to operate properly for a minimum number of read cycles. Since the read operation in a ferroelectric memory is destructive, this means that ferroelectric memory devices must withstand a certain number of read/restore operations, with little or no performance degradation. For instance, current manufacturing specifications call for memory device capable of 1E14 read/restore operations or more.
Accordingly, manufacturers perform life tests to determine the onset of ferroelectric memory cell fatigue and the performance degradation thereafter, in which the cell performance is characterized as a function of the number of such cycles or operations. Typically, this is done by applying an external pulse stream to a ferroelectric capacitor using a pulse generator instrument connected by probes to a test wafer. Because of the nature of ferroelectric memory cells, the pulse stream must alternatively apply positive and negative voltages to switch the dipole polarization in the ferroelectric material. This life cycling is generally limited to application of pulse waveforms of frequencies in the range of about 1 MHz or less, due to the capacitive loading effects of the external probes. However, this frequency limitation of conventional fatigue testing setups causes the test to extend for an unacceptably long time. In one example, with a stress pulse at about 1 MHz, testing can take as long as 28,000 hours to simulate 1E14 read/restore cycles.
This limitation renders conventional test setups and methodologies unfit for in-line testing of ferroelectric memory devices in a production setting. In this regard, it is desirable to ascertain whether a given manufacturing process flow for fabricating ferroelectric memory devices is producing memory cells capable of withstanding a certain number of read/restore cycles in near real time, in order to determine whether processing adjustments are needed. However, process personnel cannot wait for hundreds or thousands of hours to obtain this type of information. Consequently, there is a need for improved apparatus and methods for fatigue testing ferroelectric memory devices, by which these and other limitations of the current testing techniques may be mitigated or overcome.